1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having high breakdown-voltage to applied voltage.
2. Description of the Prior Art
FIG. 11 is a plan view showing a conventional semiconductor integrated circuit device disclosed in Japanese Unexamined Utility Model Publication No. 131152/1988; FIG. 12 is a sectional view of the conventional semiconductor integrated circuit device shown in FIG. 11. The semiconductor integrated circuit device will be described with an example of an npn bipolar transistor device. In FIG. 11, an insulation layer is omitted for convenience of understanding. Similarly, FIGS. 2, 5, 8, 10, 11 and 14 omit insulation layers.
In FIGS. 11 and 12, the npn bipolar transistor device, as well known, is composed of a substrate 1 consisting of a semiconductor layer 101 and an n.sup.- -type epitaxial layer 102, an n.sup.+ -type buried layer 2, a collector region 3 of an n.sup.- -type epitaxial layer formed on the substrate 1, a p-type base region 4, an element isolating region of a p.sup.+ -type diffusion layer, an insulation layer 6, a base-lead-out electrode 8 lead out through a contact hole 7, and electrode wiring 10 which is electrically connected with the base-lead-out electrode 8 through a through hole 9 and which traverses the element isolating region 5 to connect with an external terminal. The conventional npn bipolar transistor device further comprises a field plate 12 which is disposed in the insulation layer 6 above a channel region of a parasitic MOS transistor while being connected to the element isolating region 5 through a contact hole 11. The element isolating region 5 is connected to a ground terminal 13. Additionally, an emitter region and another lead-out electrode, for example, are required; but these are all omitted in the drawings because they are not essential in the explanation of the conventional device.
The operation of the conventional device will be explained below.
In the structure in which the electrode wiring 10 connected to the external terminal traverses the element isolating region 5 as shown in FIGS. 11 and 12, static electricity by which the ground terminal 13 turns to positive potential while the base region 4 turns to negative potential may be applied from outside. If the field plate 12 is not provided, when such static electricity is applied from outside, a parasitic MOS transistor in which the element isolating region 5 serves as a source, the base region 4 serves as a drain and the upper layer part of the collector region 3 serves as a channel region will be produced. However, since the conventional device is provided with the field plate 12 which blocks the collector region 3 between the element isolating region 5 and the base region 4 from the electrode wiring 10 while being connected to the element isolating region 5 which is grounded, there is formed no channel around the surface of the collector region 3 which is in contact with the insulating layer 6, so that the operation of the parasitic MOS transistor is inhibited. In this way, it is arranged that the semiconductor device should not be broken.
In the semiconductor integrated circuit device as stated above, a drop of the breakdown-voltage of the semiconductor integrated circuit device because of the parasitic MOS transistor is inhibited. However, when it is desired to enhance the voltage applied to the electrode wiring 10 close to the breakdown-voltage of the bulk of the pn-junction material as a high breakdown-voltage IC, since the field plate 12 is connected with the element isolating region 5, the field plate 12 will be at ground potential to have a large difference in potential from the electrode wiring 10, and the potential in the surface of the collector region 3 will change rapidly under the edge of the field plate 12 which the electrode wiring 10 traverses. As a result, a concentration of the electric field in the collector region 3 under the edge of the field plate 12 will be more significant than in the remaining collector region and the boundary region between the element isolating region 5 and the collector region 3, and there will be arise the problem that the breakdown-voltage of the semiconductor integrated circuit device cannot be enhanced close to the breakdown-voltage of the substrate thereof.
The drop of the breakdown-voltage as stated above is not necessarily caused merely in bipolar transistor devices but in diode devices, as shown in FIGS. 13 and 14, which have a structure where an element isolation is effected by the pn junction while a field plate disposed in an insulation layer is connected to an element isolating region.
Referring to FIGS. 13 and 14, an n.sup.+ -type semiconductor region 21 is disposed close to the surface of the substrate 1 consisting of a semiconductor layer 101 and an n.sup.- -type epitaxial layer 102 connected to the semiconductor layer 101. In order to isolate semiconductor active elements, an element isolating region 5 of p.sup.+ -type diffusion layer is disposed in a substrate 1. An insulation layer 6 is disposed on the surfaces of the substrate 1 and element isolating region 5. A contact hole 22 is provided in the insulation layer 6 on the n.sup.+ -type semiconductor region 21, and electrode wiring 10 is formed on the insulation layer 6 to traverse the element isolating region 5 and connected electrically with the semiconductor region 21 through the contact hole 22. In the insulation layer 6, a field plate 12 buried so as to be in contact with the surface of the element isolating region 5 through a contact hole 11 is disposed along the electrode wiring 10 so that it blocks the element isolating region 5 and the boundary region between the element isolating region 5 and the substrate 1 from the electrode wiring 10. The element isolating region 5 is at ground potential, while voltage V.sub.B is applied to the n.sup.+ -type semiconductor region 21 through the electrode wiring 10.
Assuming that a high breakdown-voltage diode technique which employs a thin epitaxial layer disclosed in the U.S. Pat. No. 4,292,642 is used in manufacturing a junction diode and that there is no electrode wiring 10 traversing the element isolating region 5 through insulation layer 6 in the diode device, the breakdown-voltage of the diode device is determined depending on the breakdown-voltage at the junction surface of the semiconductor layer 101 with the n.sup.- -type epitaxial layer 102 in the substrate 1. For example, when the resistivity and the thickness of the n.sup.- -type epitaxial layer 102 is 5.OMEGA. cm and 15 .mu.m respectively and the resistivity of the semiconductor layer 101 is 40.OMEGA. cm, the breakdown-voltage of the diode is approximately 650 V.
Thus, when, in the diode device originally having the breakdown-voltage of about 650 V, the electrode wiring 10 traversing the p.sup.+ -type element isolating region 5 through the insulation layer 6 as shown in FIGS. 13 and 14 is provided while the field plate 12 buried in the insulation layer 6 is connected to the surface of the element isolating region 5 through the contact hole 11, the field plate 12 comes to be at ground potential to have a large difference in potential from the electrode wiring 10, and the potential at the surface of the n.sup.- -type epitaxial layer 102 under the edge of the field plate 12 which the electrode wiring 10 traverses rapidly changes. As a result, a concentration of the electric field at the surface of the epitaxial layer 102 under the edge of the field plate 12 becomes more significant than in the boundary region between the element isolating region 5 and the epitaxial layer 102, so that the breakdown-voltage of the diode device drops. For example, the breakdown-voltage under the conditions that the insulation layer 6 under the field plate 12 has the thickness t.sub.01 of 1 .mu.m while the insulation layer 6 under the electrode wiring 10 has the thickness t.sub.02 of 3 .mu.m, is approximately 430 V, and this is a drop of about 220 V comparing with a case where the electrode wiring 10 does not traverse the element isolating region 5. FIG. 15 shows the relations between the thickness t.sub.01 and the breakdown-voltage under the above conditions.
The drop of the breakdown-voltage because of the structure where the element isolation is effected by the pn junction while the field plate in the insulation layer is connected to the element isolating region is a general problem in a semiconductor integrated circuit device.